Allwinner A20 - Page 281

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 281 / 812
Offset: 0xFC
Register Name: PH_CFG0
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
000: Input 001: Output
010: LCD1_D1 011: Reserved
100: UART3_RX 101: Reserved
110: EINT1 111: CSI1_D1
3
/
/
/
2:0
R/W
0
PH0_SELECT
000: Input 001: Output
010: LCD1_D0 011: Reserved
100: UART3_TX 101: Reserved
110: EINT0 111: CSI1_D0
1.19.4.65. PH CONFIGURE REGISTER 1
Offset: 0x100
Register Name: PH_CFG1
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31
/
/
/
30:28
R/W
0
PH15_SELECT
000: Input 001: Output
010: LCD1_D15 011: ETXD2
100: KP_IN5 101: SMC_VPPPP
110: EINT15 111: CSI1_D15
27
/
/
/
26:24
R/W
0
PH14_SELECT
000: Input 001: Output
010: LCD1_D14 011: ETXD3
100: KP_IN4 101: SMC_VPPEN
110: EINT14 111: CSI1_D14
23
/
/
/
22:20
R/W
0
PH13_SELECT
000: Input 001: Output
010: LCD1_D13 011: Reserved