Allwinner A20 - Page 321

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 321 / 812
Bit
Read/W
rite
Default/H
ex
Description
31:24
R/W
0
IDMA_FCALPHA
Alpha
23:16
R/W
0
IDMA_FCRED
Red
15:8
R/W
0
IDMA_FCGREEN
Green
7:0
R/W
0
IDMA_FCBLUE
Blue
3.1.4.11. COLOR SPACE CONVERTER 0 CONTROL REGISTER
Offset: 0x74
Register Name: MP_CSC0CTL_REG
Bit
Read/W
rite
Default/He
x
Description
31:8
/
/
/
7:4
R/W
0
CSC0_DATAMOD
Data mode control
0:
Interleaved AYUV8888 mode
1:
Interleaved YUV422 mode
In mode 0 and mode 1, only the channel 0 data path is valid
for this module, the channel 1 data flow will by-pass the csc0
module, and direct to input formatter 1.
2:
Planar YUV422 mode (UV combined only)
3:
Planar YUV420 mode (UV combined only)
4:
Planar YUV411 mode (UV combined only)
In mode 2/3/4, following rule:
----Y component data transfer through channel 0, and UV
component data transfer through channel 1.