Allwinner A20 - Page 331

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 331 / 812
Offset: 0xBC
Register Name: MP_ROPIDX1CTL_REG
Bit
Read/W
rite
Default/H
ex
Description
7:channel 0’ sub channel 1’ in byte
8:channel 0’ sub channel 1’ in word (32bit)
Other: Reserved
5
R/W
0
NOD3_CTL
Index 1 node3 setting ( channel 2’ not logic )
0:by-pass
1:not
4
R/W
0
NOD2_CTL
Index 1 node2 setting ( channel 1’ not logic )
0:by-pass
1:not
3
R/W
0
NOD1_CTL
Index 1 node1 setting ( channel 0’ not logic)
0:by-pass
1:not
2:0
R/W
0
NOD0_CTL
Index 1 node0 setting ( sorting control )
0:012
1:021
2:102
3:120
4:201
5:210
Other: Reserved
Note: the result of the add or multiply operation will select the high 8 (byte operation) or 32bits (word
operation).
3.1.4.22. ALPHA / COLOR KEY CONTROL REGISTER
Offset: 0xC0
Register Name: MP_ALPHACKCTL_REG
Bit
Read/W
rite
Default/
Hex
Description
31:11
/
/
/
10
R/W
0
CK_REDCON