A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 359 / 812
CSI Channel_0 FIFO 1 output buffer-A address register
CSI Channel_0 FIFO 1 output buffer-B address register
CSI Channel_0 FIFO 2 output buffer-A address register
CSI Channel_0 FIFO 2 output buffer-B address register
CSI Channel_0 output buffer control register
CSI Channel_0 status register
CSI Channel_0 interrupt enable register
CSI Channel_0 interrupt status register
CSI Channel_0 horizontal size register
CSI Channel_0 vertical size register
CSI Channel_0 line buffer length register
CSI Channel_1 FIFO 0 output buffer-A address register
CSI Channel_1 FIFO 0 output buffer-B address register
CSI Channel_1 FIFO 1 output buffer-A address register
CSI Channel_1 FIFO 1 output buffer-B address register
CSI Channel_1 FIFO 2 output buffer-A address register
CSI Channel_1 FIFO 2 output buffer-B address register
CSI Channel_1 output buffer control register
CSI Channel_1 status register
CSI Channel_1 interrupt enable register
CSI Channel_1 interrupt status register
CSI Channel_1 horizontal size register
CSI Channel_1 vertical size register
CSI Channel_1 line buffer length register
CSI Channel_2 FIFO 0 output buffer-A address register
CSI Channel_2 FIFO 0 output buffer-B address register
CSI Channel_2 FIFO 1 output buffer-A address register
CSI Channel_2 FIFO 1 output buffer-B address register
CSI Channel_2 FIFO 2 output buffer-A address register
CSI Channel_2 FIFO 2 output buffer-B address register
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