Allwinner A20 - Page 394

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 394 / 812
Offset Address: 0X0004
Register Name: CSI1_CFG_REG
Bit
Read/W
rite
Default/
Hex
Description
15:12
/
/
/
11:10
R/W
0
FIELD_SEL
Field selection. Applies to CCIR656 interface only.
00: start capturing with field 1.
01: start capturing with field 2.
10: start capturing with either field.
11: reserved
09:08
R/W
2
INPUT_SEQ
Input data sequence, only valid for YUV422 mode.
00: YUYV
01: YVYU
10: UYVY
11: VYUY
07:05
/
/
/
4
R/W
0
FPS_DS
Fps down sample(failed, no this code)
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames
3
R/W
0
FIELD_POL
Field polarity
0: negative(field=0 indicate odd, field=1 indicate even )
1: positive(field=1 indicate odd, field=0 indicate even )
This register is not applied to CCIR656 interface.
02
R/W
1
VREF_POL
Vref polarity
0: negative
1: positive
This register is not applied to CCIR656 interface.
01
R/W
0
HERF_POL
Href polarity
0: negative
1: positive
This register is not applied to CCIR656 interface.
00
R/W
1
CLK_POL