Allwinner A20 - Page 440

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 440 / 812
Offset: 0x004
Register name: Ctrl
Bit
Read/
Write
Default/
Hex
Description
1
R/W
0
CLR_AVMUTE:
General control packet Clear_AVMUTE flag
0
R/W
0
SET_AVMUTE:
General control packet Set_AVMUTE flag
5.2.4.3. INTERRUPT STATUS REGISTER
Offset: 0x008
Register name: Int_Status
Bits
Read
/Write
Default
/Hex
Description
31:23
/
/
reserved
22
R/W
0
AUD_FIFO_UNDER_FLOW Mask
0: interrupt disable
1: interrupt enable
21
R/W
0
AUD_FIFO_OVER_FLOW Mask
0: interrupt disable
1: interrupt enable
20
R/W
0
AUD_TRANS_BUSY Mask
0: interrupt disable
1: interrupt enable
19:18
-
-
-
17
R/W
0
VID_FIFO_OVER_FLOW Mask
0: interrupt disable
1: interrupt enable
16
R/W
0
VID_FIFO_UNDER_FLOW Mask
0: interrupt disable
1: interrupt enable
15:7
/
/
reserved
6
R/Clea
r
0
AUD_FIFO_UNDER_FLOW
Audio input fifo under flow flag
0: normal
1: under flow happen