Allwinner A20 - Page 445

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 445 / 812
5.2.4.9. VIDEO TIMING REGISTER3
Offset: 0x020
Register name: VID_Timing_3
Bits
Read
/Write
Default
/Hex
Description
31:28
/
/
reserved
27:16
R/W
0
VID_VSPW:
Vertical sync plus width is:
VID_VSPW+1 TMDS clock
15:12
/
/
reserved
11:0
R/W
0
VID_HSPW:
Horizontal sync plus width is:
VID_HSPW+1 TMDS clock
5.2.4.10. VIDEO TIMING REGISTER4
Offset: 0x024
Register name: VID_Timing_4
Bits
Read
/Write
Default
/Hex
Description
31:26
/
/
reserved
25:16
R/W
0
TX_CLOCK
Note: normal 10’b11_1110_0000
15:2
/
/
reserved
1
R/W
0
VID_VSYNC_ACTIVE_SEL:
Vsync priority selection
0: active low
1: active high
0
R/W
0
VID_HSYNC_ACTIVE_SEL:
Hsync priority selection
0: active low
1: active high