Allwinner A20 - Page 557

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 557 / 812
Offset: 0x920
Register Name: DEBE_IYUVCTL_REG
Bit
Read/W
rite
Default/
Hex
Description
1: enable
5.4.4.27. SOURCE DATA INPUT DATA PORTS
Input buffer channel
Planar YUV
Interleaved YUV
Channel0
Y
YUV
Channel1
U
-
Channel2
V
-
5.4.4.28. DE BACKEND YUV CHANNEL FRAME BUFFER ADDRESS REGISTER
Offset:
Channel 0 : 0x930
Channel 1 : 0x934
Channel 2 : 0x938
Register Name: DEBE_IYUVADD_REG
Bit
Read/W
rite
Default/
Hex
Description
31:0
R/W
UDF
IYUV_ADD
Buffer Address
Frame buffer address in BYTE
5.4.4.29. DE BACKEND YUV CHANNEL BUFFER LINE WIDTH REGISTER
Offset:
Channel 0 : 0x940
Channel 1 : 0x944
Channel 2 : 0x948
Register Name: DEBE_IYUVLINEWIDTH_REG