EasyManua.ls Logo

Allwinner A20 - Page 687

Allwinner A20
812 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 687 / 812
3:0
R/W
R
0x0
in the PCED, through bit 0 to bit 3 must be zero in this field.
6.8.7.12. HCBULKCURRENTED REGISTER
Offset: 0x42c
Register Name: HcBulkCurrentED [BCED]
Default Value: 0x0
Bit
Read/Write
Default
Description
HCD
HC
31:4
R/W
R/W
0x0
BulkCurrentED[31:4]
This is advanced to the next ED after the HC has served the
present one. HC continues processing the list from where it left off
in the last Frame. When it reaches the end of the Bulk list, HC
checks the ControlListFilled of HcControl. If set, it copies the
content of HcBulkHeadED to HcBulkCurrentED and clears the bit.
If it is not set, it does nothing. HCD is only allowed to modify this
register when the BulkListEnable of HcControl is cleared. When
set, the HCD only reads the instantaneous value of this register.
This is initially set to zero to indicate the end of the Bulk list.
3:0
R/W
R/W
0x0
BulkCurrentED [3:0]
Because the general TD length is 16 bytes, the memory structure
for the TD must be aligned to a 16-byte boundary. So the lower bits
in the PCED, through bit 0 to bit 3 must be zero in this field.
6.8.7.13. HCDONEHEAD REGISTER
Offset: 0x430
Register Name: HcDoneHead
Default Value:0x0
Bit
Read/Write
Default
Description
HCD
HC
31:4
R
R/W
0x0
HcDoneHead[31:4]
When a TD is completed, HC writes the content of HcDoneHead to
the NextTD field of the TD. HC then overwrites the content of
HcDoneHead with the address of this TD. This is set to zero
whenever HC writes the content of this register to HCCA. It also
sets the WritebackDoneHead of HcInterruptStatus.
3:0
R
R/W
0x0
HcDoneHead[3:0]
Because the general TD length is 16 bytes, the memory structure
for the TD must be aligned to a 16-byte boundary. So the lower bits
in the PCED, through bit 0 to bit 3 must be zero in this field.
6.8.7.14. HCFMINTERVAL REGISTER
Offset: 0x434
Register Name: HcFmInterval Register
Default Value:0x2edf
Bit
Read/Write
Default
Description
HCD
HC

Table of Contents