Allwinner A20 - Page 729

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 729 / 812
Offset: 0x00
Register Name: AC_CTL
Default Value: 0x0000_0000
Bit
Read/Wr
ite
Default
Description
16
R
0
RX_STATUS
RX Transfer Status
0: PCM IN
1: MIC IN
15:10
/
/
/
9
R/W
0
RX_MODE
RX MODE
0: PCM IN
1: MIC IN
Note: this bit indicate which mode will be selected when PCM IN
and MIC IN slots are available simultaneity
8
R/W
0
ASS
Audio sample select with TX FIFO under run
0: sending 0 (invalid frame)
1: sending the last audio (valid frame)
7
R/W
0
TXEN
0: Disable
1: Enable
6
R/W
0
RXEN
0: Disable
1: Enable
5
R/W
0
AC-link EN
0: Disable
1: Enable(SYNC signal transfer to Codec)
4
R/W
0
GEN
Globe Enable
A disable on this bit overrides any other block or channel enables
and flushes all FIFOs.
0: Disable
1: Enable
3:2
/
/
/
1
R/W
0
WARM_RST
Warm reset