Allwinner A20 - Page 76

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 76 / 812
Offset: 0x108
Register Name: BE1_CLK_REG
Bit
Read/
Write
Default/Hex
Description
00: PLL3
01: PLL7
10: PLL5
11: /.
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from
1 to 16.
1.5.4.46. DE-FE 0 CLOCK(DEFAULT: 0X00000000)
Offset: 0x10C
Register Name: FE0_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.
30
R/W
0x0
FE0_RST.
DE-FE0 Reset.
0: reset valid, 1: reset invalid.
29:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: PLL3
01: PLL7
10: PLL5
11: /.
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from