Allwinner A20 - Page 789

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 789 / 812
Offset: 0x00
Register Name:
CAN_MOD_SEL
Default Value: 0x0000_0001
Bit
Read/Write
Default
Description
transmitted or received is aborted and Reset Mode is entered.
0 - Normal operation. The controller returns to Operating Mode
6.16.5.2. CAN COMMAND REGISTER
Offset: 0x04
Register Name:
CAN_CMD_REG
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:6
/
/
/
5
W
0
BUS_OFF
Bus off Request
Set this bit to 1 to initial a CPU-driven BUS OFF event.
4
W
0
SELF_REQ
Self Reception Request
Set this bit to 1 to make a message to be transmitted and
received simultaneously
3
W
0
CLR_OR_FLAG
Clear Data Overrun Flag
Set this bit to 1 to clear the data overrun flag signaled by the
data overrun status bit.
Note: No further data overrun interrupt will be generated while
data overrun status bit remains set
2
W
0
REL_RX_BUF
Release Rx Buffer
Set this bit to 1 to release receive buffer
1
W
0
ABT_REQ
Abort Request
Set this bit to 1 to request to abort the current message
transmission
0
W
0
TRANS_REQ
Transmission Request
Set this bit to 1 to request to transmit a message