Allwinner A20 - Page 94

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 94 / 812
Offset: 0x1F4
Register Name: CLK_OUTB_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
CLK_OUT_EN
Clock Output Enable
0: disable
1: Clock Output Enable
OutputB = Clock Source / DIVIDOR-N / DIVIDOR-M.
30:26
/
/
/
25:24
R/W
0x0
CLK_OUT_SRC_SEL
00: OSC24MHz/750=32KHz
01: Losc
10: OSC24MHz
11: /
23:22
/
/
/
21:20
R/W
0x0
DIVIDOR_N
Clock Output Divide Factor N
00: /1
01: /2
10: /4
11: /8
19:13
/
/
/
12:8
R/W
0x0
DIVIDOR_M
Clock Output Divide Factor M
00000: /1
00001: /2
00010: /3
……
11111: /32
7:0
/
/
/