ARM Cortex-A53 MPCore - Page 100

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-39
ID021414 Non-Confidential
4.3.19 AArch64 Debug Feature Register 0, EL1
The ID_AA64DFR0_EL1 characteristics are:
Purpose Provides top level information of the debug system in the AArch64
Execution state.
Usage constraints This register is accessible as follows:
Configurations ID_AA64DFR0_EL1 is architecturally mapped to external register
ID_AA64DFR0.
Attributes ID_AA64DFR0_EL1 is a 64-bit register.
Figure 4-18 shows the ID_AA64DFR0_EL1 bit assignments.
Figure 4-18 ID_AA64DFR0_EL1 bit assignments
Table 4-47 shows the ID_AA64DFR0_EL1 bit assignments.
To access the ID_AA64DFR0_EL1:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
438712 1116 1520 1924 2328 27
063
RES
0
RES
0 DebuggerTraceverPMUverBRPsWRPsCTX_CMPs
RES
0
32 31
Table 4-47 ID_AA64DFR0_EL1 bit assignments
Bits Name Function
[63:32] - Reserved,
RES0.
[31:28] CTX_CMPs Number of breakpoints that are context-aware, minus 1. These are the highest numbered
breakpoints:
0b0001 Two breakpoints are context-aware.
[27:24] - Reserved,
RES0.
[23:20] WRPs The number of watchpoints minus 1:
0b0003 Four watchpoints.
[19:16] - Reserved,
RES0.
[15:12] BRPs The number of breakpoints minus 1:
0b0005 Six breakpoints.
[11:8] PMUver Performance Monitors extension version.
0b0001 Performance monitor system registers implemented, PMUv3.
[7:4] Tracever Trace extension:
0b0000 Trace system registers not implemented.
[3:0] Debugger Debug architecture version:
0b0110 ARMv8-A debug architecture implemented.