ARM Cortex-A53 MPCore - Interfaces

Introduction
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 1-6
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1.4 Interfaces
The Cortex-A53 processor has the following external interfaces:
• Memory interface that implements either an ACE or CHI interface.
• Optional Accelerator Coherency Port (ACP) that implements an AXI slave interface.
• Debug interface that implements an APB slave interface.
• Trace interface that implements an ATB interface.
•CTI.
• Design for Test (DFT).
• Memory Built-In Self Test (MBIST).
• Q-channel, for power management.
See Interfaces on page 2-7 for more information on each of these interfaces.