Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-13
ID021414 Non-Confidential
A.10 CHI interface signals
This section describes the CHI interface signals:
• Clock and configuration signals.
• Transmit request virtual channel signals.
• Transmit response virtual channel signals on page A-14.
• Transmit data virtual channel signals on page A-14.
• Receive snoop virtual channel signals on page A-14.
• Receive response virtual channel signals on page A-14.
• Receive data virtual channel signals on page A-15.
• System address map signals on page A-15.
This interface exists only if the Cortex-A53 processor is configured to have the CHI interface.
A.10.1 Clock and configuration signals
Table A-10 shows the clock and configuration signals.
A.10.2 Transmit request virtual channel signals
Table A-11 shows the transmit request virtual channel signals.
Table A-10 Clock and configuration signals
Signal Direction Description
SCLKEN Input CHI interface bus clock enable
SINACT Input CHI snoop active
NODEID[6:0] Input Cortex-A53 CHI Node Identifier
RXSACTIVE Input Receive pending activity indicator
TXSACTIVE Output Transmit pending activity indicator
RXLINKACTIVEREQ Input Receive link active request
RXLINKACTIVEACK Output Receive link active acknowledge
TXLINKACTIVEREQ Output Transmit link active request
TXLINKACTIVEACK Input Transmit link active acknowledge
REQMEMATTR[7:0] Output Request memory attributes
Table A-11 Transmit request virtual channel signals
Signal Direction Description
TXREQFLITPEND Output Transmit request flit pending
TXREQFLITV Output Transmit request flit valid
TXREQFLIT[99:0] Output Transmit request flit payload
TXREQLCRDV Input Transmit request link-layer credit valid
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