Generic Timer
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10.3 Generic Timer register summary
A set of Generic Timer registers are allocated within each core. The Generic Timer registers are
either 32-bits wide or 64-bits wide and accessible in the AArch32 and AArch64 Execution
states.
10.3.1 AArch64 Generic Timer register summary
Table 10-2 shows the AArch64 Generic Timer registers. See the ARM
®
Architecture Reference
Manual ARMv8, for ARMv8-A architecture profile for information about these registers.
Table 10-2 AArch64 Generic Timer registers
Name Op0 CRn Op1 CRm Op2 Reset Width Description
CNTKCTL_EL1 3 c14 0 c1 0
-
a
32-bit Counter-timer Kernel Control register
CNTFRQ_EL0 3 c0 0 UNK 32-bit Counter-timer Frequency register
CNTPCT_EL0 1 UNK 64-bit Counter-timer Physical Count register
CNTVCT_EL0 2 UNK 64-bit Counter-timer Virtual Count register
CNTP_TVAL_EL0 c2 0 UNK 32-bit Counter-timer Physical Timer TimerValue
register
CNTP_CTL_EL0 1
-
b
32-bit Counter-timer Physical Timer Control
register
CNTP_CVAL_EL0 2 UNK 64-bit Counter-timer Physical Timer
CompareValue register
CNTV_TVAL_EL0 c3 0 UNK 32-bit Counter-timer Virtual Timer TimerValue
register
CNTV_CTL_EL0 1
b
32-bit Counter-timer Virtual Timer Control register
CNTV_CVAL_EL0 2 UNK 64-bit Counter-timer Virtual Timer CompareValue
register
CNTVOFF_EL2 4 c0 3 UNK 64-bit Counter-timer Virtual Offset register
CNTHCTL_EL2 c1 0
-
c
32-bit Counter-timer Hypervisor Control register
CNTHP_TVAL_EL2 c2 0 UNK 32-bit Counter-timer Hypervisor Physical Timer
TimerValue register
CNTHP_CTL_EL2 1
b
32-bit Counter-timer Hypervisor Physical Timer
Control register
CNTHP_CVAL_EL2 2 UNK 64-bit Counter-timer Hypervisor Physical Timer
CompareValue register
CNTPS_TVAL_EL1 7 c2 0 UNK 32-bit Counter-timer Physical Secure Timer
TimerValue register
CNTPS_CTL_EL1 1
-
b
32-bit Counter-timer Physical Secure Timer
Control register
CNTPS_CVAL_EL1 2 UNK 64-bit Counter-timer Physical Secure Timer
CompareValue register
a. The reset value for bits[9:8, 2:0] is
b00000
.
b. The reset value for bit[0] is 0.