Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-25
ID021414 Non-Confidential
11.8 Memory-mapped register descriptions
This section describes the Cortex-A53 processor debug registers. The Memory-mapped debug
register summary on page 11-21 provides cross-references to the individual registers.
11.8.1 External Debug Integration Mode Control Register
The EDITCTRL characteristics are:
Purpose Enables the external debug to switch from its default mode into integration
mode, where test software can control directly the inputs and outputs of
the processor, for integration testing or topology detection.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations EDITCTRL is in the processor power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-8 shows the EDITCTRL bit assignments.
Figure 11-8 EDITCTRL bit assignments
Table 11-12 shows the EDITCTRL bit assignments.
The EDITCTRL can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xF00
.
11.8.2 External Debug Device ID Register 0
The EDDEVID characteristics are:
Purpose Provides extra information for external debuggers about features of the
debug implementation.
Off DLK OSLK EDAD SLK Default
--- - RORW
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