ARM Cortex-A53 MPCore - Page 426

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-24
ID021414 Non-Confidential
0xFBC EDDEVARCH RO 32 External Debug Device Architecture Register
0xFC0 EDDEVID2 RO 32 External Debug Device ID Register 2, RES0
0xFC4 EDDEVID1 RO 32 External Debug Device ID Register 1 on page 11-26
0xFC8 EDDEVID RO 32 External Debug Device ID Register 0 on page 11-25
0xFCC EDDEVTYPE RO 32 External Debug Device Type Register
0xFD0 EDPIDR4 RO 32 Peripheral Identification Register 0 on page 11-28
0xFD4-0xFDC EDPIDR5-7 RO 32 Peripheral Identification Register 5-7 on page 11-31
0xFE0 EDPIDR0 RO 32 Peripheral Identification Register 0 on page 11-28
0xFE4 EDPIDR1 RO 32 Peripheral Identification Register 1 on page 11-28
0xFE8 EDPIDR2 RO 32 Peripheral Identification Register 2 on page 11-29
0xFEC EDPIDR3 RO 32 Peripheral Identification Register 3 on page 11-30
0xFF0 EDCIDR0 RO 32 Component Identification Register 0 on page 11-32
0xFF4 EDCIDR1 RO 32 Component Identification Register 1 on page 11-33
0xFF8 EDCIDR2 RO 32 Component Identification Register 2 on page 11-33
0xFFC EDCIDR3 RO 32 Component Identification Register 3 on page 11-34
Table 11-11 Memory-mapped debug register summary (continued)
Offset Name Type Width Description