Level 2 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-3
ID021414 Non-Confidential
7.2 Snoop Control Unit
The Cortex-A53 processor supports between one and four individual cores with L1 Data cache
coherency maintained by the SCU. The SCU is clocked synchronously and at the same
frequency as the cores.
The SCU maintains coherency between the individual data caches in the processor using ACE
modified equivalents of MOESI state, as described in Data Cache Unit on page 2-4.
The SCU contains buffers that can handle direct cache-to-cache transfers between cores without
having to read or write any data to the external memory system. Cache line migration enables
dirty cache lines to be moved between cores, and there is no requirement to write back
transferred cache line data to the external memory system.
Each core has tag and dirty RAMs that contain the state of the cache line. Rather than access
these for each snoop request the SCU contains a set of duplicate tags that permit each coherent
data request to be checked against the contents of the other caches in the cluster. The duplicate
tags filter coherent requests from the system so that the cores and system can function efficiently
even with a high volume of snoops from the system.
When an external snoop hits in the duplicate tags a request is made to the appropriate core.
7.2.1 Bus interface configuration signals
The Cortex-A53 processor implements the following bus interface configuration signals:
• BROADCASTINNER.
• BROADCASTOUTER.
• BROADCASTCACHEMAINT.
• SYSBARDISABLE (ACE only).
Table 7-1 shows the permitted combinations of these signals and the supported configurations
in the Cortex-A53 processor, with an ACE bus.
Table 7-1 Supported ACE configurations
Signal
Feature
AXI3 mode
a
ACE non-coherent
b
ACE outer coherent ACE inner coherent
No L3
cache
With L3
cache
No L3
cache
With L3
cache
No L3
cache
With L3
cache
BROADCASTCACHEMAINT 0 010101
BROADCASTOUTER 0 001111
BROADCASTINNER 0 000011
a. SYSBARDISABLE must be set to HIGH in AXI3 mode.
b. ACE non-coherent is compatible with connecting to an ACE-Lite interconnect.
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