ARM Cortex-A53 MPCore - Domain Access Control Register

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-92
ID021414 Non-Confidential
Table 4-85 shows the VTCR_EL2 bit assignments.
To access the VTCR_EL2:
MRS <Xt>, VTCR_EL2 ; Read VTCR_EL2 into Xt
MSR VTCR_EL2, <Xt> ; Write Xt to VTCR_EL2
4.3.51 Domain Access Control Register
The DACR32_EL2 characteristics are:
Purpose Allows access to the AArch32 DACR register from AArch64 state only.
Its value has no effect on execution in AArch64 state.
Table 4-85 VTCR_EL2 bit assignments
Bits Name Function
[31] - Reserved,
RES1.
[30:19] - Reserved,
RES0.
[18:16] PS Physical Address Size. The possible values are:
0b000 32 bits, 4 GB.
0b001 36 bits, 64 GB.
0b010 40 bits, 1 TB.
All other values are reserved.
[15:14] TG0 Granule size for the corresponding VTTBR_EL2.
0b00 4 KB.
0b10 64 KB.
[13:12] SH0 Shareability attribute for memory associated with translation table walks using VTTBR_EL2.
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer Shareable.
0b11 Inner Shareable.
[11:10] ORGN0 Outer cacheability attribute for memory associated with translation table walks using
VTTBR_EL2.
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0 Inner cacheability attribute for memory associated with translation table walks using
VTTBR_EL2.
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6] SL0 Starting level of the VTCR_EL2 addressed region.
[5:0] T0SZ
The size offset of the memory region addressed by VTTBR_EL2. The region size is 2
(64-T0SZ)
bytes.