ARM Cortex-A53 MPCore - Aarch64 Register Summary

System Control
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4.2 AArch64 register summary
This section gives a summary of the system registers in the AArch64 Execution state. For more
information on using the system registers, see the ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile.
The following subsections describe the system registers by functional group:
• AArch64 identification registers.
• AArch64 exception handling registers on page 4-5.
• AArch64 virtual memory control registers on page 4-6.
• AArch64 other system control registers on page 4-7.
• AArch64 performance monitor registers on page 4-7.
• AArch64 reset registers on page 4-8.
• AArch64 secure registers on page 4-9.
• AArch64 virtualization registers on page 4-9.
• AArch64 GIC system registers on page 4-10.
• AArch64 Generic Timer registers on page 4-11.
• AArch64 thread registers on page 4-11.
• AArch64 implementation defined registers on page 4-12.
• AArch64 address registers on page 4-13.
4.2.1 AArch64 identification registers
Table 4-1 shows the identification registers in AArch64 state. Bits[63:32] are reset to
0x00000000
for all 64-bit registers in Table 4-1.
Table 4-1 AArch64 identification registers
Name Type Reset Width Description
MIDR_EL1 RO
0x410FD032 32 Main ID Register, EL1 on page 4-14
MPIDR_EL1 RO
-
a
64 Multiprocessor Affinity Register on page 4-15
REVIDR_EL1 RO 0x00000000 32 Revision ID Register on page 4-16
ID_PFR0_EL1 RO
0x00000131 32 AArch32 Processor Feature Register 0 on page 4-17
ID_PFR1_EL1 RO
0x10011011
b
32 AArch32 Processor Feature Register 1 on page 4-18
ID_DFR0_EL1 RO
0x03010066 32 AArch32 Debug Feature Register 0 on page 4-19
ID_AFR0_EL1 RO
0x00000000 32 AArch32 Auxiliary Feature Register 0 on page 4-21
ID_MMFR0_EL1 RO
0x10101105 32 AArch32 Memory Model Feature Register 0 on page 4-21
ID_MMFR1_EL1 RO
0x40000000 32 AArch32 Memory Model Feature Register 1 on page 4-22
ID_MMFR2_EL1 RO
0x01260000 32 AArch32 Memory Model Feature Register 2 on page 4-24
ID_MMFR3_EL1 RO
0x02102211 32 AArch32 Memory Model Feature Register 3 on page 4-26
ID_ISAR0_EL1 RO
0x02101110 32 AArch32 Instruction Set Attribute Register 0 on page 4-28
ID_ISAR1_EL1 RO
0x13112111 32 AArch32 Instruction Set Attribute Register 1 on page 4-29
ID_ISAR2_EL1 RO
0x21232042 32 AArch32 Instruction Set Attribute Register 2 on page 4-30
ID_ISAR3_EL1 RO
0x01112131 32 AArch32 Instruction Set Attribute Register 3 on page 4-33