Programmers Model
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 3-4
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3.2 ARMv8-A architecture concepts
This section introduces both the ARMv8 architectural concepts and the associated terminology.
The following sections describe the ARMv8 architectural concepts. Each section introduces the
corresponding terms that are used to describe the architecture:
• Execution state.
• Exception levels on page 3-5.
• Security state on page 3-6.
• Rules for changing execution state on page 3-7.
• Stack pointer selection on page 3-7.
• ARMv8 security model on page 3-8.
• Instruction set state on page 3-10.
• AArch32 execution modes on page 3-10.
A thorough understanding of the terminology defined in this section is a prerequisite for reading
the remainder of this manual.
3.2.1 Execution state
The execution state defines the processor execution environment, including:
• Supported register widths.
• Supported instruction sets.
• Significant aspects of:
— The execution model.
—The Virtual Memory System Architecture (VMSA).
— The programmers model.
The execution states are:
AArch64 The 64-bit execution state. This execution state:
• Features 31 64-bit general purpose registers, with a 64-bit Program
Counter (PC), Stack Pointer (SP), and Exception Link Registers (ELRs).
• Provides a single instruction set, A64. For more information, see
Instruction set state on page 3-10.
• Defines the ARMv8 exception model, with four exception levels,
EL0-EL3, that provide an execution privilege hierarchy.
• Features Virtual Addresses (VAs) held in 64-bit registers. The Cortex-A53
VMSA implementation maps these to 40-bit Physical Address (PA) maps.
• Defines a number of PSTATE elements that hold processor state. The A64
instruction set includes instructions that operate directly on various
PSTATE elements.
• Names each system register using a suffix that indicates the lowest
exception level at which the register can be accessed.
AArch32 The 32-bit execution state. This execution state is backwards-compatible with
implementations of the ARMv7-A architecture profile that include the Security
Extensions and the Virtualization Extensions:
• Features 13 32-bit general purpose registers, and a 32-bit PC, SP, and link
register (LR). Some of these registers have multiple banked instances for
use in different processor modes.
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