ARM Cortex-A53 MPCore - Page 53

Programmers Model
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 3-3
ID021414 Non-Confidential
3.1.2 Memory model
The Cortex-A53 processor views memory as a linear collection of bytes numbered in ascending
order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second
stored word.
The processor can store words in memory as either:
• Big-endian format.
• Little-endian format.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for
more information about big-endian and little-endian memory systems.
Note
Instructions are always little-endian.
3.1.3 Jazelle implementation
The Cortex-A53 processor supports a trivial Jazelle implementation. This means:
• Jazelle state is not supported.
•The
BXJ instruction behaves as a BX instruction.
In the trivial Jazelle implementation, the processor does not accelerate the execution of any
bytecodes, and the JVM uses software routines to execute all bytecodes. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for information.
3.1.4 Modes of operation
In AArch32, the processor has the following instruction set operating states controlled by the T
bit and J bit in the CPSR.
A32 The processor executes 32-bit, word-aligned A32 instructions.
T32 The processor executes 16-bit and 32-bit, halfword-aligned T32
instructions.
The J bit and the T bit determine the instruction set used by the processor. Table 3-1 shows the
encoding of these bits.
Note
• The processor does not support Jazelle state. This means there is no processor state where
the J bit is 1 and T bit is 0.
• The processor does not support T32EE state. This means there is no processor state where
the J bit is 1 and T bit is 1.
• Transition between A32 and T32 instruction set states does not affect the processor mode
or the register contents.
Table 3-1 CPSR J and T bit encoding
J T Instruction set state
00A32
01T32