ARM Cortex-A53 MPCore - B.1 Use of R15 by Instruction

Cortex-A53 Processor AArch32 unpredictable Behaviors
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B.1 Use of R15 by Instruction
Specification
All uses of R15 as a named register specifier for a source register that is described as
UNPREDICTABLE in the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A
architecture profile pseudo-code, or in other places in the ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile, read 0 unless otherwise stated in section 4.28, or as
described in the following paragraph.
If the use of R15 as a base register for a load or store is
UNPREDICTABLE, the value used by the
load or store using R15 as a base register is the Program Counter (PC) with its usual offset and,
in the case of T32 instructions, with the forced word alignment. In this case, if the instruction
specifies Writeback, then the load or store is performed without Writeback.
Implementation
The Cortex-A53 processor does not implement a Read 0 policy on
UNPREDICTABLE use of R15
by instruction. Instead, the Cortex-A53 processor takes an
UNDEFINED exception trap.