Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-13
ID021414 Non-Confidential
6.7 Direct access to internal memory
The Cortex-A53 processor provides a mechanism to read the internal memory used by the
Cache and TLB structures through
IMPLEMENTATION-DEFINED system registers. This
functionality can be useful when investigating issues where the coherency between the data in
the cache and data in system memory is broken.
When the processor is using AArch64, the appropriate memory block and location are selected
using a number of write-only registers and the data is read from read-only registers as shown in
Table 6-5. These operations are available only in EL3. In all other modes, executing these
instruction results in an Undefined Instruction exception.
When the processor is using AArch32, the appropriate memory block and location are selected
using a number of write-only CP15 registers and the data is read from read-only CP15 registers
as shown in Table 6-5. These operations are available only in EL3. In all other modes, executing
the CP15 instruction results in an Undefined Instruction exception.
Table 6-4 AArch64 registers used to access internal memory
Function Access Operation Rd Data
Data Register 0 Read-only
MRS <Xd>, S3_3_c15_c0_0
Data
Data Register 1 Read-only
MRS <Xd>, S3_3_c15_c0_1
Data
Data Register 2 Read-only
MRS <Xd>, S3_3_c15_c0_2
Data
Data Register 3 Read-only
MRS <Xd>, S3_3_c15_c0_3
Data
Data Cache Tag Read Operation Register Write-only
MSR S3_3_c15_c2_0, <Xd>
Set/Way
Instruction Cache Tag Read Operation Register Write-only
MSR S3_3_c15_c2_1, <Xd>
Set/Way
Data Cache Data Read Operation Register Write-only
MSR S3_3_c15_c4_0, <Xd>
Set/Way/Offset
Instruction Cache Data Read Operation Register Write-only
MSR S3_3_c15_c4_1, <Xd>
Set/Way/Offset
TLB Data Read Operation Register Write-only
MSR S3_3_c15_c4_2, <Xd>
Index/Way
Table 6-5 AArch32 CP15 registers used to access internal memory
Function Access CP15 operation Rd Data
Data Register 0 Read-only
MRC p15, 3, <Rd>, c15, c0, 0
Data
Data Register 1 Read-only
MRC p15, 3, <Rd>, c15, c0, 1
Data
Data Register 2 Read-only
MRC p15, 3, <Rd>, c15, c0, 2
Data
Data Register 3 Read-only
MRC p15, 3, <Rd>, c15, c0, 3
Data
Data Cache Tag Read Operation Register Write-only
MCR p15, 3, <Rd>, c15, c2, 0
Set/Way
Instruction Cache Tag Read Operation Register Write-only
MCR p15, 3, <Rd>, c15, c2, 1
Set/Way
Data Cache Data Read Operation Register Write-only
MCR p15, 3, <Rd>, c15, c4, 0
Set/Way/Offset
Instruction Cache Data Read Operation Register Write-only
MCR p15, 3, <Rd>, c15, c4, 1
Set/Way/Offset
TLB Data Read Operation Register Write-only
MCR p15, 3, <Rd>, c15, c4, 2
Index/Way
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