ARM Cortex-A53 MPCore - ACE Interface Signals

Signal Descriptions
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A.11 ACE interface signals
This section describes the ACE master interface signals:
• Clock and configuration signals.
• Write address channel signals on page A-18.
• Write data channel signals on page A-18.
• Write data response channel signals on page A-19.
• Read address channel signals on page A-19.
• Read data channel signals on page A-20.
• Coherency address channel signals on page A-20.
• Coherency response channel signals on page A-20.
• Coherency data channel handshake signals on page A-21.
• Read and write acknowledge signals on page A-21.
For a complete description of the ACE interface signals, see the ARM
®
AMBA
®
AXI and ACE
Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.
Note
• This interface exists only if the Cortex-A53 processor is configured to have the ACE
interface.
• All ACE channels must be balanced with respect to CLKIN and timed relative to
ACLKENM.
A.11.1 Clock and configuration signals
Table A-18 shows the clock and configuration signals for the ACE interface.
Table A-18 Clock and configuration signals
Signal Direction Description
ACLKENM Input ACE Master bus clock enable. See Clocks on page 2-9 for more information.
ACINACTM Input Snoop interface is inactive and not participating in coherency:
0 Snoop interface is active.
1 Snoop interface is inactive.
SYSBARDISABLE Input Disable broadcasting of barriers onto the system bus:
0 Barriers are broadcast onto the system bus. This requires an AMBA4 ACE, or
AMBA5 CHI, interconnect.
1 Barriers are not broadcast onto the system bus. This is compatible with an
AXI3 interconnect and most AMBA4 interconnects.
a
This pin is sampled only during reset of the Cortex-A53 processor.
RDMEMATTR[7:0] Output Read request memory attributes.
WRMEMATTR[7:0] Output Write request memory attributes.
a. See Barriers on page 7-11.