ARM Cortex-A53 MPCore - Memory-Mapped Register Descriptions

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-26
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12.8 Memory-mapped register descriptions
This section describes the Cortex-A53 processor PMU registers accessible through the
memory-mapped and debug interfaces. Table 12-15 on page 12-23 provides cross-references to
individual registers.
12.8.1 Performance Monitor Configuration Register
The PMCFGR characteristics are:
Purpose Contains PMU specific configuration data.
Usage constraints The accessibility to the PMCFGR by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMCFGR is in the processor power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-8 shows the PMCFGR bit assignments.
Figure 12-8 PMCFGR bit assignments
Table 12-16 shows the PMCFGR bit assignments.
Off DLK OSLK EPMAD SLK Default
Error Error Error Error RO RO
31 17 16 15 14 13 8 7 0
N
EX
CCD
CC
RES
0 Size
Table 12-16 PMCFGR bit assignments
Bits Name Function
[31:17] - Reserved,
RES0.
[16] EX Export supported. The value is:
1 Export is supported. PMCR_EL0.EX is read/write.
[15] CCD Cycle counter has pre-scale. The value is:
1 PMCR_EL0.D is read/write.
[14] CC Dedicated cycle counter supported. The value is:
1 Dedicated cycle counter is supported.
[13:8] Size Counter size. The value is:
0b111111 64-bit counters.
[7:0] N Number of event counters. The value is:
0x06 Six counters.