Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-27
ID021414 Non-Confidential
The PMCFGR can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xE00
.
12.8.2 Peripheral Identification Registers
The Peripheral Identification Registers provide standard information required for all
components that conform to the ARM PMUv3 architecture. There is a set of eight registers,
listed in register number order in Table 12-17.
Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the
eight Peripheral ID Registers define a single 64-bit Peripheral ID.
The Peripheral ID registers are:
• Peripheral Identification Register 0.
• Peripheral Identification Register 1 on page 12-28.
• Peripheral Identification Register 2 on page 12-29.
• Peripheral Identification Register 3 on page 12-30.
• Peripheral Identification Register 4 on page 12-30.
• Peripheral Identification Register 5-7 on page 12-31.
Peripheral Identification Register 0
The PMPIDR0 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMPIDR0 can be accessed through the internal memory-mapped
interface and the external debug interface.
The accessibility to the PMPIDR0 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMPIDR0 is in the Debug power domain.
Table 12-17 Summary of the Peripheral Identification Registers
Register Value Offset
Peripheral ID4
0x04 0xFD0
Peripheral ID5
0x00 0xFD4
Peripheral ID6
0x00 0xFD8
Peripheral ID7
0x00 0xFDC
Peripheral ID0
0xD3 0xFE0
Peripheral ID1
0xB9 0xFE4
Peripheral ID2
0x2B 0xFE8
Peripheral ID3
0x00 0xFEC
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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