ARM Cortex-A53 MPCore - ACP Interface Signals

Signal Descriptions
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A.12 ACP interface signals
This section describes the ACP interface signals:
• Clock and configuration signals.
• Write address channel signals.
• Write data channel signals on page A-23.
• Write response channel signals on page A-23.
• Read address channel signals on page A-23.
• Read data channel signals on page A-24.
Note
• This interface exists only if the Cortex-A53 processor is configured to have the ACP
interface.
• All ACP channels must be balanced with respect to CLKIN and timed relative to
ACLKENS.
A.12.1 Clock and configuration signals
Table A-28 shows the clock and configuration signals for the ACP interface.
A.12.2 Write address channel signals
Table A-29 shows the write address channel signals for the ACP interface.
Table A-28 Clock and Configuration signals
Signal Direction Description
ACLKENS Input AXI slave bus clock enable.
AINACTS Input ACP master is inactive and is not participating in coherency. There must be no outstanding transactions
when the master asserts this signal, and while it is asserted the master must not send any new transactions:
0 ACP Master is active.
1 ACP Master is inactive.
Note
This signal must be asserted before the processor enters the low power L2 WFI state.
Table A-29 Write address channel signals
Signal Direction Description
AWREADYS Output Write address ready
AW VA LID S Input Write address valid
AWIDS[4:0] Input Write address ID
AWADDRS[39:0] Input Write address
AWLENS[7:0] Input Write burst length