Level 2 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-2
ID021414 Non-Confidential
7.1 About the L2 memory system
The L2 memory system consists of an:
• Integrated Snoop Control Unit (SCU), connecting up to four cores within a cluster. The
SCU also has duplicate copies of the L1 Data cache tags for coherency support. The L2
memory system interfaces to the external memory system with either an AMBA 4 ACE
bus or an AMBA 5 CHI bus. All bus interfaces are 128-bits wide.
• Optional tightly-coupled L2 cache that includes:
— Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB.
— Fixed line length of 64 bytes.
— Physically indexed and tagged cache.
— 16-way set-associative cache structure.
— Optional ACP interface if an L2 cache is configured.
— Optional ECC protection.
The L2 memory system has a synchronous abort mechanism and an asynchronous abort
mechanism, see External aborts handling on page 7-18.
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