Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-2
ID021414 Non-Confidential
2.1 About the Cortex-A53 processor functions
Figure 2-1 shows a top-level functional diagram of the Cortex-A53 processor.
Figure 2-1 Cortex-A53 processor block diagram
The following sections describe the main Cortex-A53 processor components and their
functions:
• Instruction Fetch Unit.
• Data Processing Unit on page 2-3.
• Advanced SIMD and Floating-point Extension on page 2-3.
• Cryptography Extension on page 2-4.
• Translation Lookaside Buffer on page 2-4.
• Data side memory system on page 2-4.
• L2 memory system on page 2-5.
• Cache protection on page 2-6.
• Debug and trace on page 2-6.
2.1.1 Instruction Fetch Unit
The Instruction Fetch Unit (IFU) contains the instruction cache controller and its associated
linefill buffer. The Cortex-A53 MPCore instruction cache is 2-way set associative and uses
Virtually Indexed Physically Tagged (VIPT) cache lines holding up to 16 A32 instructions, 16
32-bit T32 instructions, 16 A64 instructions, or up to 32 16-bit T32 instructions.
The IFU cannot hold A64, A32, and T32 instructions in the same cache line. For example, if the
IFU fetches both A32 and T32 instructions from the same 64 byte region of memory, that region
occupies two cache lines, one for the A32 instructions and one for the T32 instructions.
The instruction cache has the following features:
• Pseudo-random cache replacement policy.
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