System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-135
ID021414 Non-Confidential
4.4 AArch32 register summary
In AArch32 state you access the system registers through a conceptual coprocessor, identified
as CP15, the System Control Coprocessor. Within CP15, there is a top-level grouping of system
registers by a primary coprocessor register number, c0-c15. See the ARM
®
Architecture
Reference Manual ARMv8, for ARMv8-A architecture profile for more information about using
the conceptual System Control Coprocessor in a VMSA context.
The system register space includes System operations system registers and System operations.
The description of the system register space describes the permitted access, RO, WO, or RW, to
each register or operation.
The following sections describe the CP15 system control registers grouped by CRn order, and
are accessed by the MCR and MRC instructions.
• c0 registers on page 4-137.
• c1 registers on page 4-138.
• c2 registers on page 4-139.
• c3 registers on page 4-139.
• c4 registers on page 4-139.
• c5 registers on page 4-140.
• c6 registers on page 4-140.
• c7 registers on page 4-140.
• c9 registers on page 4-141.
• c10 registers on page 4-142.
• c11 registers on page 4-142.
• c12 registers on page 4-142.
• c13 registers on page 4-144.
• c14 registers on page 4-144.
• c15 registers on page 4-146.
The following subsection describes the 64-bit registers and provides cross-references to
individual register descriptions:
• 64-bit registers on page 4-147.
In addition to listing the CP15 system registers by CRn ordering, the following subsections
describe the CP15 system registers by functional group:
• AArch32 Identification registers on page 4-148.
• AArch32 Virtual memory control registers on page 4-149.
• AArch32 Fault handling registers on page 4-150.
• AArch32 Other System control registers on page 4-150.
• AArch32 Address registers
on page 4-150.
• AArch32 Thread registers on page 4-151.
• AArch32 Performance monitor registers on page 4-151.
• AArch32 Secure registers on page 4-152.
• AArch32 Virtualization registers on page 4-153.
• AArch32 GIC system registers on page 4-154.
• AArch32 Generic Timer registers on page 4-155.
• AArch32 Implementation defined registers on page 4-156.
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