ARM Cortex-A53 MPCore - Memory-Mapped Register Summary

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-21
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11.7 Memory-mapped register summary
Table 11-11 shows the offset address for the registers that are accessible from the internal
memory-mapped interface or the external debug interface. For those registers not described in
this chapter, see the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture
profile.
Table 11-11 Memory-mapped debug register summary
Offset Name Type Width Description
0x000-0x01C --Reserved
0x020 EDESR RW 32 External Debug Event Status Register
0x024 EDECR RW 32 External Debug Execution Control Register
0x028-0x02C - - - Reserved
0x030 EDWAR[31:0] RO 64 External Debug Watchpoint Address Register
0x034 EDWAR[63:32]
0x038-0x07C - - - Reserved
0x080 DBGDTRRX_EL0 RW 32 Debug Data Transfer Register, Receive
0x084 EDITR WO 32 External Debug Instruction Transfer Register
0x088 EDSCR RW 32 External Debug Status and Control Register
0x08C DBGDTRTX_EL0 RW 32 Debug Data Transfer Register, Transmit
0x090 EDRCR WO 32 External Debug Reserve Control Register
0x094 EDACR RW 32 External Debug Auxiliary Control Register
0x098 EDECCR RW 32 External Debug Exception Catch Control Register
0x09C --32Reserved
0x0A0 EDPCSRlo RO 32 External Debug Program Counter Sample Register, low word
0x0A4 EDCIDSR RO 32 External Debug Context ID Sample Register
0x0A8 EDVIDSR RO 32 External Debug Virtual Context Sample Register
0x0AC EDPCSRhi RO 32 External Debug Program Counter Sample Register, high word
0x0B0-0x2FC - - - Reserved
0x300 OSLAR_EL1 WO 32 OS Lock Access Register
0x304-0x30C - - - Reserved
0x310 EDPRCR RW 32 External Debug Power/Reset Control Register
0x314 EDPRSR RO 32 External Debug Processor Status Register
0x318-0x3FC - - -- Reserved
0x400 DBGBVR0_EL1[31:0] RW 64 Debug Breakpoint Value Register 0
0x404 DBGBVR0_EL1[63:32]
0x408 DBGBCR0_EL1 RW 32 Debug Breakpoint Control Registers, EL1 on page 11-8