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ARM Cortex-A53 MPCore - Power Management Signals

ARM Cortex-A53 MPCore
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Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-9
ID021414 Non-Confidential
A.7 Power management signals
Table A-6 shows the non-Retention power management signals.
Table A-7 on page A-10 shows the Retention power management signals.
Table A-6 Non-Retention power management signals
Signal Direction Description
CLREXMONREQ Input Clearing of the external global exclusive monitor request. When this signal is asserted,
it acts as a WFE wake-up event to all the cores in the MPCore device. See CLREXMON
request and acknowledge signaling on page 2-20 for more information.
CLREXMONACK Output Clearing of the external global exclusive monitor acknowledge. See CLREXMON
request and acknowledge signaling on page 2-20 for more information.
EVENTI Input Event input for processor wake-up from WFE state. See Event communication using
WFE or SEV on page 2-25 for more information.
EVENTO Output Event output. Active when a
SEV
instruction is executed. See Event communication using
WFE or SEV on page 2-25 for more information.
STANDBYWFI[CN:0] Output Indicates whether a core is in WFI low-power state:
0
Core not in WFI low-power state.
1
Core in WFI low-power state. This is the reset condition.
STANDBYWFE[CN:0] Output Indicates whether a core is in WFE low-power state:
0
Core not in WFE low-power state.
1
Core in WFE low-power state.
STANDBYWFIL2 Output Indicates whether the L2 memory system is in WFI low-power state. This signal is active
when the following conditions are met:
All cores are in WFI low-power state, held in reset, or nL2RESET is asserted
LOW.
In an ACE configuration, ACINACTM is asserted HIGH.
In a CHI configuration, SINACT is asserted HIGH.
If ACP has been configured, AINACTS is asserted HIGH.
L2 memory system is idle.
L2FLUSHREQ Input L2 hardware flush request.
L2FLUSHDONE Output L2 hardware flush complete.
SMPEN[CN:0] Output Indicates whether a core is taking part in coherency.
DBGNOPWRDWN[CN:0] Output Processor no powerdown request
0
Do not request that the processor stays powered up.
1
Request that the processor stays powered up.
DBGPWRUPREQ[CN:0] Output Processor powerup request
0
Do not request processor to power up.
1
Request that the processor is not powered up.
DBGPWRDUP[CN:0] Input Processor powered up
0
Processor is powered down.
1
Processor is powered up.

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