System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-47
ID021414 Non-Confidential
4.3.26 Cache Type Register
The CTR_EL0 characteristics are:
Purpose Provides information about the architecture of the caches.
Usage constraints This register is accessible as follows:
This register is accessible at EL0 when SCTLR_EL1.UCT is set to 1.
Configurations CTR_EL0 is architecturally mapped to AArch32 register CTR. See Cache
Type Register on page 4-188.
Attributes CTR_EL0 is a 32-bit register.
Figure 4-24 shows the CTR_EL0 bit assignments.
Figure 4-24 CTR_EL0 bit assignments
Table 4-59 shows the CTR_EL0 bit assignments.
To access the CTR_EL0:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config RO RO RO RO RO
Table 4-59 CTR_EL0 bit assignments
Bits Name Function
[31] - Reserved,
RES1.
[30:28] - Reserved,
RES0.
[27:24] CWG Cache Write-Back granule. Log
2
of the number of words of the maximum size of memory that can be
overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:
0x4
Cache Write-Back granule size is 16 words.
[23:20] ERG Exclusives Reservation Granule. Log
2
of the number of words of the maximum size of the reservation granule
that has been implemented for the Load-Exclusive and Store-Exclusive instructions:
0x4
Exclusive reservation granule size is 16 words.
[19:16] DminLine Log
2
of the number of words in the smallest cache line of all the data and unified caches that the processor
controls:
0x4
Smallest data cache line size is 16 words.
[15:14] L1lp L1 Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:
0b10
Virtually Indexed Physically Tagged (VIPT).
[13:4] - Reserved,
RES0.
[3:0] IminLine Log
2
of the number of words in the smallest cache line of all the instruction caches that the processor controls.
0x4
Smallest instruction cache line size is 16 words.
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