System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-46
ID021414 Non-Confidential
• The cache type, either instruction or data cache.
Usage constraints This register is accessible as follows:
Configurations CSSELR_EL1 is architecturally mapped to AArch32 register
CSSELR(NS). See Cache Size Selection Register on page 4-187.
Attributes CSSELR_EL1 is a 32-bit register.
Figure 4-23 shows the CSSELR_EL1 bit assignments.
Figure 4-23 CSSELR_EL1 bit assignments
Table 4-57 shows the CSSELR_EL1 bit assignments.
To access the CSSELR_EL1:
MRS <Xt>, CSSELR_EL1 ; Read CSSELR_EL1 into Xt
MSR CSSELR_EL1, <Xt> ; Write Xt to CSSELR_EL1
Register access is encoded as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
Table 4-57 CSSELR_EL1 bit assignments
Bits Name Function
[31:4] - Reserved,
RES0
[3:1]
Level
a
a. The combination of Level=
0b001
and InD=
1
is
reserved.
Cache level of required cache:
0b000
L1.
0b001
L2.
0b010
-
0b111
Reserved.
[0]
InD
a
Instruction not Data bit:
0
Data or unified cache.
1
Instruction cache.
Table 4-58 CSSELR_EL1 access encoding
op0 op1 CRn CRm op2
11 010 0000 0001 000
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