ARM Cortex-A53 MPCore - About the Programmers Model

Programmers Model
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3.1 About the programmers model
The Cortex-A53 processor implements the ARMv8-A architecture. This includes:
• Support for all the Exception levels, EL3-EL0.
• Support for both Execution states, AArch64 and AArch32, at each Exception level.
• The following instruction sets:
AArch64 Execution state
The A64 instruction set.
AArch32 Execution state
The T32 and A32 instruction sets.
• Optionally, an implementation can include one or more of:
— The Advanced SIMD and Floating-point instructions, in all instruction sets.
— The Cryptography Extension, that provides additional instructions in all instruction
sets.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for
more information.
This section describes:
• Advanced SIMD and Floating-point support.
• Memory model on page 3-3.
• Jazelle implementation on page 3-3.
• Modes of operation on page 3-3.
3.1.1 Advanced SIMD and Floating-point support
Advanced SIMD is a media and signal processing architecture that adds instructions targeted
primarily at audio, video, 3-D graphics, image, and speech processing.
Floating-point performs single-precision and double-precision floating-point operations.
Note
Advanced SIMD, its associated implementations, and supporting software, are commonly
referred to as NEON.
All scalar floating-point instructions are available in the A64 instruction set. All VFP
instructions are available in the A32 and T32 instruction sets.
The same Advanced SIMD instructions are available in both the A32 and T32 instruction sets.
The A64 instruction set offers additional Advanced SIMD instructions, including
double-precision floating-point vector operations.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for
more information.
See the ARM
®
Cortex
®
-A53 MPCore Processor Advanced SIMD and Floating-point Extension
Technical Reference Manual for implementation-specific information.