Debug
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11.3 AArch64 debug register summary
Table 11-3 summarizes debug control registers that are accessible in the AArch64 Execution
state. These registers are accessed by the
MRS
and
MSR
instructions in the order of Op0, CRn, Op1,
CRm, Op2.
See the Memory-mapped register summary on page 11-21 for a complete list of registers
accessible from the internal memory-mapped or the external debug interface. The 64-bit
registers cover two addresses on the external memory interface. For those registers not
described in this chapter, see the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A
architecture profile.
Table 11-3 AArch64 debug register summary
Name Type Reset Width Description
OSDTRRX_EL1 RW - 32 Debug Data Transfer Register, Receive, External View
DBGBVR0_EL1 RW - 64 Debug Breakpoint Value Register 0
DBGBCR0_EL1 RW - 32 Debug Breakpoint Control Registers, EL1 on page 11-8
DBGWVR0_EL1 RW - 64 Debug Watchpoint Value Register 0
DBGWCR0_EL1 RW - 32 Debug Watchpoint Control Registers, EL1 on page 11-11
DBGBVR1_EL1 RW - 64 Debug Breakpoint Value Register 1
DBGBCR1_EL1 RW - 32 Debug Breakpoint Control Registers, EL1 on page 11-8
DBGWVR1_EL1 RW - 64 Debug Watchpoint Value Register 1
DBGWCR1_EL1 RW - 32 Debug Watchpoint Control Registers, EL1 on page 11-11
MDCCINT_EL1 RW
0x00000000
32 Monitor Debug Comms Channel Interrupt Enable Register
MDSCR_EL1 RW - 32 Monitor Debug System Register
DBGBVR2_EL1 RW - 64 Debug Breakpoint Value Register 2
DBGBCR2_EL1 RW - 32 Debug Breakpoint Control Registers, EL1 on page 11-8
DBGWVR2_EL1 RW - 64 Debug Watchpoint Value Register 2
DBGWCR2_EL1 RW - 32 Debug Watchpoint Control Registers, EL1 on page 11-11
OSDTRTX_EL1 RW - 32 Debug Data Transfer Register, Transmit, External View
DBGBVR3_EL1 RW - 64 Debug Breakpoint Value Register 3
DBGBCR3_EL1 RW - 32 Debug Breakpoint Control Registers, EL1 on page 11-8
DBGWVR3_EL1 RW - 64 Debug Watchpoint Value Register 3
DBGWCR3_EL1 RW - 32 Debug Watchpoint Control Registers, EL1 on page 11-11
DBGBVR4_EL1 RW - 64 Debug Breakpoint Value Register 4
DBGBCR4_EL1 RW - 32 Debug Breakpoint Control Registers, EL1 on page 11-8
DBGBVR5_EL1 RW - 64 Debug Breakpoint Value Register 5
DBGBCR5_EL1 RW - 32 Debug Breakpoint Control Registers, EL1 on page 11-8
OSECCR_EL1 RW - 32 Debug OS Lock Exception Catch Register
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