ARM Cortex-A53 MPCore - ACE and CHI Interface Signals

Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-12
ID021414 Non-Confidential
A.9 ACE and CHI interface signals
Table A-9 shows the interface signals that both ACE and CHI use.
Table A-9 ACE and CHI interface signals
Signal Direction Description
BROADCASTCACHEMAINT
a
Input Enable broadcasting of cache maintenance operations to downstream caches:
0 Cache maintenance operations are not broadcast to downstream
caches.
1 Cache maintenance operations are broadcast to downstream
caches.
This pin is sampled only during reset of the Cortex-A53 processor.
BROADCASTINNER
a
Input Enable broadcasting of Inner Shareable transactions:
0 Inner Shareable transactions are not broadcast externally.
1 Inner Shareable transactions are broadcast externally.
If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER
HIGH.
This pin is sampled only during reset of the Cortex-A53 processor.
BROADCASTOUTER
a
Input Enable broadcasting of outer shareable transactions:
0 Outer Shareable transactions are not broadcast externally.
1 Outer Shareable transactions are broadcast externally.
This pin is sampled only during reset of the Cortex-A53 processor.
a. See Table 7-1 on page 7-3 for more information.