ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-1
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Appendix B
Cortex-A53 Processor AArch32
UNPREDICTABLE
Behaviors
This appendix describes specific Cortex-A53 processor UNPREDICTABLE behaviors of particular
interest.
For AArch32 execution, the ARMv8-A architecture specifies a much narrower range of legal
behaviors for the cases that in ARMv7 were described as
UNPREDICTABLE. See ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. This gives
considerable background on this topic and documents these
UNPREDICTABLE behaviors in these
sections:
• A range of legal behaviors for each
UNPREDICTABLE case.
• A single preferred behavior for each
UNPREDICTABLE case from that range of legal
behaviors.
Where possible and practical, all ARM implementations adhere to these single preferred
behaviors. In some limited instances an ARM implementation might not adhere to these single
preferred behaviors, and instead behaves as described by one of the alternate legal behaviors.
The purpose of this appendix is to document all such instances where the Cortex-A53 processor
implementation diverges from the preferred behavior described in ARMv8 AArch32
UNPREDICTABLE behaviors, and to describe exactly which of the remaining alternative behaviors
is implemented.
This appendix contains the following sections:
• Use of R15 by Instruction on page B-3.
• unpredictable instructions within an IT Block on page B-4.
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