Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-8
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11.4 AArch64 debug register descriptions
This section describes the debug registers in the AArch64 Execution state. The AArch64 debug
register summary on page 11-6 provides cross-references to the individual registers.
11.4.1 Debug Breakpoint Control Registers, EL1
The DBGBCRn_EL1characteristics are:
Purpose Holds control information for a breakpoint. Each DBGBVR_EL1 is
associated with a DBGBCR_EL1 to form a Breakpoint Register Pair
(BRP). DBGBVRn_EL1 is associated with DBGBCRn_EL1 to form
BRPn.
The range of n for DBGBCRn_EL1 is 0 to 5.
Usage constraints These registers are accessible as follows:
Configurations DBGBCRn_EL1 are architecturally mapped to:
• The AArch32 DBGBCRn registers.
• The external DBGBCRn_EL1 registers.
Attributes See the register summary in Table 11-3 on page 11-6.
The debug logic reset value of a DBGBCRn_EL1 is
UNKNOWN.
Figure 11-2 shows the DBGBCRn_EL1 bit assignments.
Figure 11-2 DBGBCRn_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RWRWRW RW
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