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ARM Cortex-A53 MPCore - Auxiliary Control Register

ARM Cortex-A53 MPCore
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System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-196
ID021414 Non-Confidential
4.5.28 Auxiliary Control Register
The ACTLR characteristics are:
Purpose Controls write access to i
MPLEMENTATION DEFINED registers in EL2, such
as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR and L2ACTLR.
Usage constraints This register is accessible as follows:
Configurations The processor does not implement the ACTLR (NS) register. This register
is always
RES0. It is mapped to AArch64 register ACTLR_EL1. See
Auxiliary Control Register, EL1 on page 4-55.
ACTLR (S) is mapped to AArch64 register ACTLR_EL3. See Auxiliary
Control Register, EL3 on page 4-56.
Attributes ACTLR is a 32-bit register.
Figure 4-99 shows the ACTLR bit assignments.
Figure 4-99 ACTLR bit assignments
EL0
NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
--RWRWRWRW RW
RES
0
31 765 10
RES
0
432
L2ACTLR access control
L2ECTLR access control
L2CTLR access control
CPUECTLR access control
CPUACTLR access control

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