System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-197
ID021414 Non-Confidential
Table 4-194 shows the ACTLR bit assignments.
To access the ACTLR:
MRC p15, 0, <Rt>, c1, c0, 1 ; Read ACTLR into Rt
MCR p15, 0, <Rt>, c1, c0, 1 ; Write Rt to ACTLR
4.5.29 Architectural Feature Access Control Register
The CPACR characteristics are:
Purpose Controls access to CP0 to CP13, and indicates which of CP0 to CP13 are
implemented.
Usage constraints This register is accessible as follows:
The CPACR has no effect on instructions executed at EL2.
Configurations CPACR is architecturally mapped to AArch64 register CPACR_EL1. See
Architectural Feature Access Control Register on page 4-57.
Table 4-194 ACTLR bit assignments
Bits Name Function
[31:7] - Reserved,
RES0.
[6] L2ACTLR access control L2ACTLR write access control. The possible values are:
0
The register is not write accessible from a lower exception level. This
is the reset value.
1
The register is write accessible from EL2.
[5] L2ECTLR access control L2ECTLR write access control. The possible values are:
0
The register is not write accessible from a lower exception level. This
is the reset value.
1
The register is write accessible from EL2.
[4] L2CTLR access control L2CTLR write access control. The possible values are:
0
The register is not write accessible from a lower exception level. This
is the reset value.
1
The register is write accessible from EL2.
[3:2] - Reserved,
RES0.
[1] CPUECTLR access control CPUECTLR write access control. The possible values are:
0
The register is not write accessible from a lower exception level. This
is the reset value.
1
The register is write accessible from EL2.
[0] CPUACTLR access control CPUACTLR write access control. The possible values are:
0
The register is not write accessible from a lower exception level. This
is the reset value.
1
The register is write accessible from EL2.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RWRWRWRW RW
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