ARM Cortex-A53 MPCore - Features

Introduction
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 1-5
ID021414 Non-Confidential
1.3 Features
The Cortex-A53 processor includes the following features:
• Full implementation of the ARMv8-A architecture instruction set with the architecture
options listed in ARM architecture on page 1-3.
• In-order pipeline with symmetric dual-issue of most instructions.
•Harvard Level 1 (L1) memory system with a Memory Management Unit (MMU).
• Level 2 (L2) memory system providing cluster memory coherency, optionally including
an L2 cache.