System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-14
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4.3 AArch64 register descriptions
This section describes all the system registers, in register number order, when the system is in
the AArch64 Execution state. Table 4-1 on page 4-3 to Table 4-11 on page 4-12 provide
cross-references to individual registers.
4.3.1 Main ID Register, EL1
The MIDR_EL1 characteristics are:
Purpose Provides identification information for the processor, including an
implementer code for the device and a device ID number.
Usage constraints This register is accessible as follows:
Configurations The MIDR_EL1 is:
• Architecturally mapped to the AArch32 MIDR register. See Main
ID Register on page 4-157.
• Architecturally mapped to external MIDR_EL1 register.
Attributes MIDR_EL1 is a 32-bit register.
Figure 4-1 shows the MIDR_EL1 bit assignments.
Figure 4-1 MIDR_EL1 bit assignments
Table 4-13 shows the MIDR_EL1 bit assignments.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
Table 4-13 MIDR_EL1 bit assignments
Bits Name Function
[31:24] Implementer Indicates the implementer code. This value is:
0x41
ASCII character 'A' - implementer is ARM.
[23:20] Variant Indicates the variant number of the processor. This is the major revision number x in the rx part of the rxpy
description of the product revision status. This value is:
0x0
r0p2.
[19:16] Architecture Indicates the architecture code. This value is:
0xF
Defined by CPUID scheme.
[15:4] PartNum Indicates the primary part number. This value is:
0xD03
Cortex-A53 processor.
[3:0] Revision Indicates the minor revision number of the processor. This is the minor revision number y in the py part of
the rxpy description of the product revision status. This value is:
0x2
r0p2.
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