ARM Cortex-A53 MPCore - Aarch64 PMU Register Descriptions

Performance Monitor Unit
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12.4 AArch64 PMU register descriptions
This section describes the Cortex-A53 processor PMU registers in the AArch64 Execution state.
Table 12-3 on page 12-5 provides cross-references to individual registers.
12.4.1 Performance Monitors Control Register
The PMCR_EL0 characteristics are:
Purpose Provides details of the Performance Monitors implementation, including
the number of counters implemented, and configures and controls the
counters.
Usage constraints This register is accessible as follows:
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
Configurations The PMCR_EL0 is architecturally mapped to the AArch32 PMCR
register. See Performance Monitors Control Register on page 12-16.
Attributes PMCR_EL0 is a 32-bit register.
Figure 12-2 shows the PMCR_EL0 bit assignments.
Figure 12-2 PMCR_EL0 bit assignments
Table 12-4 shows the PMCR_EL0 bit assignments.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
RW RW RW RW RW RW
E
31 24 23 16 15 11 10 6 5 4 3 2 1 0
IMP IDCODE N RES0DPXDCPLC
7
Table 12-4 PMCR_EL0 bit assignments
Bits Name Function
[31:24] IMP Implementer code:
0x41 ARM.
This is a read-only field.
[23:16] IDCODE Identification code:
0x03 Cortex-A53.
This is a read-only field.
[15:11] N Number of event counters.
0b00110 Six counters.
[10:7] - Reserved,
RES0.
[6] LC Long cycle count enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded in
PMOVSR[31]. The possible values are:
0 Overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0.
1 Overflow on increment that changes PMCCNTR_EL0[63] from 1 to 0.