Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-8
ID021414 Non-Confidential
To access the PMCR_EL0:
MRS <Xt>, PMCR_EL0 ; Read PMCR_EL0 into Xt
MSR PMCR_EL0, <Xt> ; Write Xt to PMCR_EL0
To access the PMCR in AArch32 Execution state, read or write the CP15 registers with:
MRC p15, 0, <Rt>, c9, c12, 0; Read Performance Monitor Control Register
MCR p15, 0, <Rt>, c9, c12, 0; Write Performance Monitor Control Register
[5] DP Disable cycle counter, PMCCNTR_EL0 when event counting is prohibited:
0
Cycle counter operates regardless of the non-invasive debug authentication settings. This is the
reset value.
1
Cycle counter is disabled if non-invasive debug is not permitted and enabled.
This bit is read/write.
[4] X Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over
an event bus:
0
Export of events is disabled. This is the reset value.
1
Export of events is enabled.
This bit is read/write and does not affect the generation of Performance Monitors interrupts on the nPMUIRQ
pin.
[3] D Clock divider:
0
When enabled, PMCCNTR_EL0 counts every clock cycle. This is the reset value.
1
When enabled, PMCCNTR_EL0 counts every 64 clock cycles.
This bit is read/write.
[2] C Clock counter reset. This bit is WO. The effects of writing to this bit are:
0
No action. This is the reset value.
1
Reset PMCCNTR_EL0 to 0.
This bit is always RAZ.
Resetting PMCCNTR does not clear the PMCCNTR_EL0 overflow bit to 0. See the ARM
®
Architecture
Reference Manual ARMv8, for ARMv8-A architecture profile. for more information.
[1] P Event counter reset. This bit is WO. The effects of writing to this bit are:
0
No action. This is the reset value.
1
Reset all event counters, not including PMCCNTR_EL0, to zero.
This bit is always RAZ.
In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that MDCR_EL2.HPMN
reserves for EL2 use.
In EL2 and EL3, a write of 1 to this bit resets all the event counters.
Resetting the event counters does not clear any overflow bits to 0.
[0] E Enable. The possible values of this bit are:
0
All counters, including PMCCNTR_EL0, are disabled. This is the reset value.
1
All counters are enabled.
This bit is RW.
In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that MDCR_EL2.HPMN
reserves for EL2 use.
On Warm reset, the field resets to 0.
Table 12-4 PMCR_EL0 bit assignments (continued)
Bits Name Function
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