Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-4
ID021414 Non-Confidential
11.2 Debug register interfaces
The processor implements the ARMv8 Debug architecture and debug events as described in the
ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
The Debug architecture defines a set of debug registers. The debug register interfaces provide
access to these registers from:
• Software running on the processor.
• An external debugger.
This section describes:
• Processor interfaces.
• Effects of resets on debug registers.
• External access permissions on page 11-5.
11.2.1 Processor interfaces
System register access allows the processor to directly access certain debug registers. The
external debug interface, see External debug interface on page 11-37, enables both external and
self-hosted debug agents to access debug registers. Access to the debug registers is partitioned
as follows:
Debug registers
This function is system register based and memory-mapped. You can access the
debug register map using the APB slave port. See External debug interface on
page 11-37.
Performance monitor
This function is system register based and memory-mapped. You can access the
performance monitor registers using the APB slave port. See External debug
interface on page 11-37.
Trace registers
This function is memory-mapped. See External debug interface on page 11-37.
Cross Trigger Interface registers
This function is debug register based and memory-mapped. See Chapter 14 Cross
Trigger.
11.2.2 Effects of resets on debug registers
The processor has the following reset signals that affect the debug registers:
nCPUPORESET
This signal initializes the processor logic, including the debug, Embedded Trace
Macrocell (ETM) trace unit, breakpoint, watchpoint logic, and performance
monitors logic. This maps to a cold reset that covers reset of the processor logic
and the integrated debug functionality.
nCORERESET
This signal resets some of the debug and performance monitor logic. This maps
to a warm reset that covers reset of the processor logic.
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