System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-2
ID021414 Non-Confidential
4.1 About system control
The system registers control and provides status information for the functions implemented in
the processor. The main functions of the system registers are:
• Overall system control and configuration.
• Memory Management Unit (MMU) configuration and management.
• Cache configuration and management.
• System performance monitoring.
• GIC configuration and management.
The system registers are accessible in the AArch64 and AArch32 Execution states. The
execution states are described in the ARMv8-A architecture concepts on page 3-4.
The system registers accessed in the AArch64 Execution state are described in the AArch64
register descriptions on page 4-14.
The system registers accessed in the AArch32 Execution state are described in the AArch32
register descriptions on page 4-157.
Some of the system registers can be accessed through the memory-mapped or external debug
interfaces.
Bits in the system registers that are described in the ARMv7 architecture are redefined in the
ARMv8-A architecture:
• UNK/SBZP, RAZ/SBZP, and RAZ/WI are redefined as
RES0.
• UNK/SBOP and RAO/SBOP are redefined as
RES1.
RES0 and RES1 are described in the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A
architecture profile.
For more information on the execution states, see the ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile.
4.1.1 AArch32 registers affected by CP15SDISABLE
In AArch32 state, the CP15SDISABLE input disables write access to certain system registers.
The Cortex-A53 processor does not have any
IMPLEMENTATION DEFINED registers that are
affected by CP15SDISABLE.
For a list of registers affected by CP15SDISABLE, see the ARM
®
Architecture Reference
Manual ARMv8, for ARMv8-A architecture profile.
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